1. Field of the Invention
This invention relates to memory for data processing equipment and more specifically, to user configurable memory architectures for data processing equipment.
2. Description of the Prior Art
Traditional memory structures according to the Princeton or Harvard architectures, include storage capability for several data words that are each individually addressable by a central processing unit (CPU). This memory is directly accessible by having the CPU excecute an instruction that contains the address of the data to be accessed. In this manner, the CPU may either read or write data into the memory. Due to the addressing limitations of the instruction words for the CPU (i.e., the number of bit locations allocated for addresses), large volumes of data must be stored externally to the CPU memory. This is commonly done in external storage devices such a magnetic tape, hard or floppy discs. Such external devices are typically accessed by using a single address with an additional signal to load data into the CPU as a series of data words. This external memory configuration is advantgeous in that it provides storage for large bulk data that cannot be stored within the CPU addressable memory space. However, the disadvantages are that the external memory devices are inefficient for single word access and are basically much slower than the directly addressable memory of the CPU.
The object of the present invention is to provide memory that is directly accessible by the central processing unit and also memory which is accessible through the same configuration as an external memory device, but with a much faster access time. Additionally, the user is given the capability to determine which portion of the memory is directly addressable by the CPU and which portion is accessible as if it were an external peripheral.